RISC, CISC and pipelining
Two CPU philosophies
- Processors come in two design styles: CISC and RISC.
- They trade off doing more per instruction against doing each instruction faster.
- Pipelining then overlaps instructions for more speed.
CISC vs RISC
| Feature | CISC | RISC |
|---|---|---|
| Instruction set | many, complex | few, simple |
| Instruction length | variable | fixed |
| Memory access | many instructions | only load/store |
| Pipeline-friendly | harder | naturally |
| Cycles per instruction | varies | usually 1 |
- CISC (e.g. x86) does more per instruction in hardware; RISC (e.g. ARM) keeps instructions simple, fixed-length and register-to-register — longer programs but quick, predictable steps.
Practice
A RISC processor is characterised by:
RISC keeps instructions few, simple and fixed-length (usually 1 cycle); CISC has many complex variable-length ones.
Practice
In a RISC design, which instructions are allowed to access memory?
RISC is load/store: only load and store touch memory; everything else is register-to-register.
Pipelining
- A pipeline processes instructions in overlapping stages (Fetch → Decode → Execute → Memory → Write back), like an assembly line.
- Each stage works on a different instruction, so once full, one instruction completes per cycle.
- RISC's fixed-length instructions make every stage take the same time.
- A hazard can stall it: a data hazard (a result isn't ready yet) or a control hazard (a branch makes the next address unknown).
Practice
When a pipeline is full, it completes about:
Overlapping the stages means a new instruction finishes each cycle once the pipeline is full.
Practice
A pipeline "data hazard" happens when:
A data hazard stalls the pipeline because a needed result is still being computed. (A control hazard comes from a branch.)
You've got it
Key idea
- CISC = many complex variable-length instructions; RISC = few simple fixed-length, load/store only
- RISC suits pipelining (predictable stages) and uses many fast registers
- a pipeline overlaps stages → ~one instruction completes per cycle
- pipelines stall on data and control hazards